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specification for lcd module model no. TM128160GKFWG prepared by: date: checked by : date: verified by : date: approved by: date: tianma microelectronics co., ltd ver. 1.0
1/26 rev.1.0 revision record date ver. ref. page revision no. revision items
2/26 rev.1.0 1 general specifications : contents item main lcd sub lcd unit lcd type color stn oled --- lcd duty 1/160 1/40 --- lcd bias 1/10 --- --- viewing direction 6:00 --- o?clock glass area(wxh) 36.25x49.80 26.8x21.2 mm viewing area(wxh) 32.05x40.20 21.374x10.338 mm active area(wxh) 29.56x36.95 19.374x8.338 mm number of dots 128(r+g+b)x160 96x32(b)+96x7(y) mm dote size(wxh) 0.221x0.221 0.182x0.182 mm dot pitch(wxh) 0.231x0.231 0.202x0.202 mm controller hd66766 ssd1301 --- vbat 3.6~4.5v(typ) lcd operating voltage 16.8 9 v outline dimensions refer to outline drawing on next page backlight led(white) --- --- operating temperat -20---+70 ?? -20---+60 ?? --- storage temperature -30---+80 ?? -40---+85 ?? --- weight tbd --- data transfer 8 bit parallel i 2 c --- polarizer mode transmissive /negative --- ---
3 / 26 r e v . 1 . 0 2 outline
3. circuit block diagram / 4 / 2 6 rev.1.0
5/26 rev.1.0 4 absolute maximum ratings(ta=25 ?? ) main_lcd item sym bol min. max. unit rem a rk power supply voltage vdd - vss -0.3 +4.6 lcd driving voltage vlcd -0.3 +20.0 v operating temperature range top -20 +70 storage temperature range tst -30 +80 ?? no condensation oled item min max unit comment supply voltage (vdd) -0.3 4 v ta=25 ?? supply voltage (vee) 0 vdd ? 16.5 v ta=25 ?? input voltage (vin) vss - 0.3 vdd + 0.3 v ta=25 ?? operating temp. -20 60 ?? storage temp -40 85 ??
6 / 2 6 rev.1.0 5. electrical specifications and instruction code (vss=0v, ta=25 ?? ) 5 . 1 e l e c t r i c a l c h a r a c t e r i s t i c s parameter symbol condition min typ max unit supply voltage for logic vbat --- 3.2 3.8 12 v supply voltage for main lcd (lcd drive) vlcd1 --- --- 16.8 --- v supply voltage for oled (oled drive) vlcd2 --- --- 9 --- v main vdd=3.0v 0.8vdd --- vdd input voltage?h? level(v ih ) sub vdd=3.0v 0.8vdd --- vdd v main vdd=3.0v 0 --- 0.2vdd input voltage?l? level(v il ) sub vdd=3.0v 0 0.2vdd v main vdd=3.0v --- --- 2.5 supply current (logic) i dd sub vdd=3.0v --- 0.5 1 ma supply voltage (led) v led --- --- 9.9 --- v supply current (led) i led --- 15.0 20.0 ma
5.2 interface signals pinno. symbo l level description 1 vbat h power supply 2 vbat h power supply 3 gnd l ground 4 disp ?arst h/l reset pin l: active 5 sda h/l i 2 c-bus data signal 6 scl h/l i 2 c-bus clock signal 7 led-en h/l led enable pin l:active 8 on-off h/l vdd on or off. h: active 9 vibrator h/l vibrator control pin. 10 lcd-cs h/l lcd chip select pin 11 rs h/l index select/data command select 12 wr h/l write operation(8080 system) 13 rd h/l read operation(8080 system) 14 db0 h/l data bus bit 0 15 db1 h/l data bus bit 1 16 db2 h/l data bus bit 2 17 db3 h/l data bus bit 3 18 db4 h/l data bus bit 4 19 db5 h/l data bus bit 5 20 db6 h/l data bus bit 6 21 db7 h/l data bus bit 7 22 sp+ h/l speak input pin(+) 23 sp- h/l speak input pin(-) 24 rec+ h/l receive input pin(+) 25 gnd l ground 26 gnd l ground 27 rec- h/l receive input pin(-) 28 led-b h/l blue led control pin 29 led-g h/l green led control pin 30 led-r h/l red led control pin 7/26 rev. 1.0
8/26 rev.1.0 5.3 interface timing chart hitach hd66766 interface protocol twrf twrr tdsw th w r t d h r v o h1 vil vih vil rs wr * rd* vih vil vih vil tas tah vil vih pwlw, pwlr pwhw, pwhr tcycw, tcycr vih vih vil vih vil db0 to db15 db0 to db15 wrire data read data v o h1 v o l1 v o l1 tddr
mpu i 2 c interface the i 2 c communication interface consists of slave address bit sa0 (d 5 ), i 2 c -bus data signal sda (d 0 for output and d 1 for input) and i 2 c -bus clock signal scl (d 4 ). both the data and clock signals must be connected to pull-up resistors. there are also five input signals including, res#, cs1#, p/s#, cs2, sp#, which is used for the initialization of device. a) slave address bit (sa0 ) ssd1301 has to recognize the slave address before transmitting or receiving any information by the i 2 c -bus. the device will respond to the slave address following by the slave address bit (?sa0? bit) and the read/write select bit (?r/w#? bit) with the fo llowing byte format, b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 1 1 1 0 sa0 r/w# ?sa0? bit provides an extension bit for the slave address. either ?0111100? or ?0111101?, can be selected as the slave address of ssd1301. ?r/w#? bit is used to determine the operation mode of the i 2 c -bus interface. r/w#=1, it is in read mode. r/w#=0, it is in write mode. b) i 2 c-bus data signal (sda) sda acts as a communication channel between the transmitter and the receiver. the data and the acknowledgement are sent through the sda. if sda in is connected to the ?sda out?, the device becomes fully i 2 c bus compatible. it should be noticed that the ito track resistance and the pulled-up resistance at ?sda? pin becomes a voltage potential divider. as a result, the acknowledgement would not be possible to attain a valid logic 0 level in ?sda?. the ?sda out? pin may be disconnected from the ?sda in? pin. with such arrangement, the acknowledgement signal will be ignored in the i 2 c -bus. c) i 2 c-bus clock signal (scl) the transmission of information in the i 2 c -bus is following a clock signal, scl. each transmission of data bit is taken place during a single clock period of scl. i 2 c -bus write data and read register status the i 2 c -bus interface gives access to write data and command into the device. please refer to figure 8 for the write mode of i 2 c -bus in chronological order. i 2 c-bus data format 0 1 1 1 sa0 p slave address m = 0 words n = 0 bytes msb ??????.lsb 1 byte write mode slave address ssd1301 slave address read mode r/w# d/c# co ack ack control byte data by te control byte ack data byte ac k s 0 1 1 1 1 0 0 1 1 1 1 0 s sa0 ack r/w# status bytes ack p sa0 r/w# co d/c # ack control byte note: co ? continuation bit d/c# ? data / command selection bit ack ? acknowledgement sa0 ? slave address bit r/w# ? read / write selection bit s ? start condition / p ? stop condition 0 0 0 0 0 0 0 1 1 1 1 0 d/c# co ack solomon ssd1301 interface 9/26 rev. 1.0
data output by receiver data output by transmitter scl from master s start condition clock pulse for acknowledgement 1 8 9 non - acknowledge 2 acknowledge s s tart condition sda scl p stop condition sda scl t hstart t sstop write mode for i 2 c 1) th e master device initiates the data communication by a start condition. the definition of the start condition is shown in figure 9. the start condition is established by pulling the sda from high to low while the scl stays high. 2) the slave address is follow ing the start condition for recognition use. for the ssd1301, the slave address is either ?b0111100? or ?b0111101? by changing the sa0 to high or low. 3) the write mode is established by setting the r/w# bit to logic ?0?. 4) an acknowledgement signal will be ge nerated after receiving one byte of data, including the slave address and the r/w# bit. please refer to the figure 10 for the graphical representation of the acknowledge signal. the acknowledge bit is defined as the sda line is pulled down during the high period of the acknowledgement related clock pulse. 5) after the transmission of the slave address, either the control byte or the data byte may be sent across the sda. a control byte mainly consists of co and d/c# bits following by six ?0? ?s. a. if the co bit is set as logic ?0?, the transmission of the following information will contain data bytes only. b. the d/c# bit determines the next data byte is acted as a command or a data. if the d/c# bit is set to logic ?0?, it defines the following data byte as a comma nd. if the d/c# bit is set to logic ?1?, it defines the following data byte as a data which will be stored at the gddram. the gddram column address pointer will be increased by one automatically after each data write. 6) acknowledge bit will be generated afte r receiving each control byte or data byte. 7) the write mode will be finished when a stop condition is applied. the stop condition is also defined in figure 9. the stop condition is established by pulling the ?sda in? from low to high while the ?scl? stays h igh. definition of the start and stop condition definition of the acknowledgement condition solomon ssd1301 interface 10/26 rev. 1.0
11/26 rev.1.0 5.4 instruction code instruction list(hd66766) upper code lower code reg. no. register name r/ w rs db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 description exe cu- tion cyc le ir index 0 0 * * * * * * * * * id6 id5 id4 id3 id2 id1 id0 sets the index register value. 0 note1 sr status read 1 0 l7 l6 l5 l4 l3 l2 l1 l0 0 c6 c5 c4 c3 c2 c1 c0 reads the driving raster-row position (l7 ? 0) and contrast setting (c6 ? 0). 0 r00h start oscillation 0 1 * * * * * * * * * * * * * * * 1 starts the oscillation mode. 10 ms note1 device code read 1 1 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 reads 0766h. 0 r01h driver output control 0 1 0 0 0 0 0 0 cm s sgs 0 0 0 nl4 nl3 nl2 nl1 nl0 sets the common driver shift direction (cms), segment driver shift direction (sgs) and driving duty ratio (nl4 ? 0). 0 r02h lcd- driving- waveform control 0 1 0 0 0 0 0 rst b/c eor 0 0 nw 5 nw 4 nw 3 nw 2 nw 1 nw 0 sets lcd drive ac waveform (b/c), and eor output (eor) or the number of n-raster-rows (nw5 ? 0) at c-pattern ac drive. 0 r03h power control 1 0 1 bs3 bs2 bs1 bs0 bt3 bt2 bt1 bt0 0 dc2 dc1 dc0 ap1 ap0 slp stb sets the sleep mode (slp), standby mode (stb), lcd power on (ap1 ? 0), boosting cycle (dc2 ? 0), boosting output multiplying factor (bt 2 ? 0), operation of voltage inverting circuit (bt3) and lcd drive bias value (bs3 ? 0). 0 r04h contrast control 0 1 0 0 0 0 0 vr2 vr1 vr0 0 ct6 ct5 ct4 ct3 ct2 ct1 ct0 sets the regulator adjustment (vr2 ? 0) and contrast adjustment (ct6 ? 0). 0 r05h entry mode 0 1 spr 0 0 0 0 0 hwm 0 0 0 i/d1 i/d0 am lg2 lg1 lg0 specifies ac counter mode (am), increment/decrement mode (i/d1 ? 0), high-speed write mode (hwm). 0 note2 r06h compare resister 0 1 cp1 5 cp1 4 cp1 3 cp1 2 cp1 1 cp1 0 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0 specifies the compare resister (cp15-0), 0 r07h display control 0 1 0 0 0 0 0 vle2 vle1 spt 0 0 0 0 b/w rev d1 d0 specifies display on (d1-0), black- and-white reversed display (rev), pixel on/off mode ( al b), screen division driving (spt) and vertical scroll .(vle2-1) 0 r0bh frame frequency control 0 1 0 0 0 0 0 0 div 1 div 0 0 0 0 0 rtn 3 rtn 2 rtn 1 rtn 0 specifies the line retrace period (rtn3 ? 0) and operating clock frequency division ratio (div1 ? 0). 0 r0ch power control 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 vc2 vc1 vc0 sets the adjustment factor for the vci voltage (vc2 ? 0). 0 r11h vertical scroll control 0 1 vl2 7 vl2 6 vl2 5 vl2 4 vl2 3 vl2 2 vl2 1 vl2 0 vl1 7 vl1 6 vl1 5 vl1 4 vl1 3 vl1 2 vl1 1 vl1 0 sets the 1 st screen display start raster - row (vl17-10) and 2 nd screen display start raster - row (vl27-20) . 0 r14h 1 st screen driving position 0 1 se 17 se 16 se 15 se 14 se 13 se 12 se 11 se 10 ss 17 ss 16 ss 15 ss 14 ss 13 ss 12 ss 11 ss 10 sets the 1 st screen driving start position (ss17 ? 10) and 1 st screen driving end position (se17 ? 10). 0 r15h 2 nd screen driving position 0 1 se 27 se 26 se 25 se 24 se 23 se 22 se 21 se 20 ss 27 ss 26 ss 25 ss 24 ss 23 ss 22 ss 21 ss 20 sets 2 nd screen driving start position (ss27 ? 20) and 2 nd screen driving end position (se27 ? 20). 0 r16h horizontal ram address position 0 1 he a 7 hea 6 hea 5 hea 4 hea 3 hea 2 hea 1 hea 0 hsa 7 hsa 6 hsa 5 hsa 4 hsa 3 hsa 2 hsa 1 hsa 0 sets start (hsa7 ? 0) and end (hea 7 ? 0) of the horizontal ram address range. 0 r17h vertical ram address position 0 1 vea 7 vea 6 vea 5 vea 4 vea 3 vea 2 vea 1 vea 0 vsa 7 vsa 6 vsa 5 vsa 4 vsa 3 vsa 2 vsa 1 vsa 0 sets start (vsa7 ? 0) and end (vea7 ? 0) of the vertical ram address range. 0 r20h ram write data mask 0 1 wm 15 wm 14 wm 13 wm 12 wm 11 wm 10 wm 9 wm 8 wm 7 wm 6 wm 5 wm 4 wm 3 wm 2 wm 1 wm 0 specifies write data mask (wm1 5 ? 0) at ram write. 0
12/26 rev.1.0 instruction list (cont.) upper code lower code reg. no. register name r/ w rs db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 description execu- tion cycle r21h ram address set 0 1 ad15 ? 8 (upper) ad 6 ? 0 (lower) initially set the ram address to the address counter (ac). 0 r22 ram data write 0 1 write data (upper) write data (lower) writes data to the ram. 0 ram data read 1 1 read data (upper) read data (lower) reads data from the ram. 0 r30h grayscale palette control (1) 0 1 0 0 pk15 pk14 pk13 pk12 pk11 pk10 0 0 pk 05 pk04 pk03 pk02 pk01 pk00 specifies the grayscale palette. 0 r31h g rayscale palette control (2) 0 1 0 0 pk35 pk34 pk33 pk32 pk31 pk30 0 0 pk25 pk24 pk23 pk22 pk21 pk20 specifies the grayscale palette. 0 r32h g rayscale palette control (3) 0 1 0 0 pk55 pk54 pk53 pk52 pk51 pk50 0 0 pk45 pk44 pk43 pk42 pk41 pk40 specifies the grayscale palette. 0 r33h g rayscale palette control (4) 0 1 0 0 pk75 pk74 pk73 pk72 pk71 pk70 0 0 pk65 pk64 pk63 pk62 pk61 pk60 specifies the grayscale palette. 0 r34h grayscale palette control ( 5 ) 0 1 0 0 pk95 pk94 pk93 pk92 pk91 pk90 0 0 pk85 pk84 pk83 pk82 pk81 pk80 specifies the grayscale palette. 0 r35h grayscale palette control ( 6 ) 0 1 0 0 pk 115 pk 114 pk 113 pk 112 pk 111 pk 110 0 0 pk 105 pk 104 pk 103 pk 102 pk 101 pk 100 specifies the grayscale palette. 0 r36h grayscale palette control ( 7 ) 0 1 0 0 pk 135 pk 134 pk 133 pk 132 pk 131 pk 130 0 0 pk 125 pk 124 pk 123 pk 122 pk 121 pk 120 specifies the grayscale palette. 0 r37h grayscale palette control ( 8 ) 0 1 0 0 pk 155 pk 154 pk 153 pk 152 pk 151 pk 150 0 0 pk 145 pk 144 pk 143 pk 142 pk 141 pk 140 specifies the grayscale palette. 0 r3 8 h grayscale palette control ( 9 ) 0 1 0 0 pk 175 pk 174 pk 173 pk 172 pk 171 pk 170 0 0 pk 165 pk 164 pk 163 pk 162 pk 161 pk 160 specifies the grayscale palette. 0 r39h grayscale palette control ( 10 ) 0 1 0 0 pk 195 pk 194 pk 193 pk 192 pk 191 pk 190 0 0 pk 185 pk 184 pk 183 pk 182 pk 181 pk 180 specifies the grayscale palette. 0 r3ah grayscale palette control ( 11 ) 0 1 0 0 pk 215 pk 214 pk 213 pk 212 pk 211 pk 210 0 0 pk 205 pk 204 pk 203 pk 202 pk 201 pk 200 specifies the grayscale palette. 0 r3bh grayscale palette control ( 12 ) 0 1 0 0 pk 235 pk 234 pk 233 pk 232 pk 231 pk 230 0 0 pk 2 2 5 pk 224 pk 223 pk 222 pk 221 pk 220 specifies the grayscale palette. 0 r3ch grayscale palette control ( 13 ) 0 1 0 0 pk 255 pk 254 pk 253 pk 252 pk 251 pk 250 0 0 pk 255 pk 244 pk 243 pk 242 pk 241 pk 240 specifies the grayscale palette. 0 r3dh grayscale palette control ( 14 ) 0 1 0 0 pk 275 pk 274 pk 273 pk 272 pk 271 pk 270 0 0 pk 265 pk 264 pk 263 pk 262 pk 261 pk 260 specifies the grayscale palette. 0 r3eh grayscale palette control ( 15 ) 0 1 0 0 pk 295 pk 294 pk 293 pk 292 pk 291 pk 290 0 0 pk 28 5 pk 284 pk 283 pk 282 pk 281 pk 280 specifies the grayscale palette. 0 r3fh grayscale palette control ( 16 ) 0 1 0 0 pk 315 pk 314 pk 313 pk 312 pk 311 pk 310 0 0 pk 305 pk 304 pk 303 pk 302 pk 301 pk 300 specifies the grayscale palette. 0 note: 1 . ? * ? means doesn ? t matter. 2. high-speed write mode is available only for the ram writing.
command table (ssd1301) command table (d/ c# =0, r/ w#(wr#)=0, e (rd# )=1) bit pattern command description 0000x 3 x 2 x 1 x 0 set lower colum n address set the lower nibble of the column address register using x 3 x 2 x 1 x 0 as data bits. the initial display line register is reset to 0000b after por. 0001x 3 x 2 x 1 x 0 set higher column address set the higher nibble of the column address register using x 3 x 2 x 1 x 0 as data bits. the initial display line register is reset to 0000b after por. 01x 5 x 4 x 3 x 2 x 1 x 0 set display start line set display ram display start line register from 0 - 63 using x 5 x 4 x 3 x 2 x 1 x 0 . display start line register is reset to 000000 during por. 10000001 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 set contrast control register double byte command to select 1 out of 256 contrast steps. contrast increases as x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 is increased from 00000000b to 11111111b. x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 =10000000b after por 1010000x 0 set segment re - map x 0 =0: column address 00h is mapped to seg0 (por) x 0 =1: column address 83h is mapped to seg0 1010010x 0 set entire display on/off x 0 =0: normal display (por) x 0 =1: entire display on 1010011x 0 set normal/inverse display x 0 =0: norma l display (por) x 0 =1: inverse display 1010111x 0 set display on/off x 0 =0: turns off oled panel (por) x 0 =1: turns on oled panel 1011x 3 x 2 x 1 x 0 set page address set gddram page address (0~8) for read/write using x 3 x 2 x 1 x 0 1100x 3 * * * set com output scan direction x 3 =0: normal mode (por) x 3 =1: remapped mode. com0 to com[n - 1] becomes com[n - 1] to com0 in multiplex ratio is equal to n. 11100000 set read - modify - write mode read - modify - write mode will be entered in which the column address will not be i ncreased during display data read. after por, read - modify - write mode is turned off 11100010 software reset initialize internal status registers 11101110 set end of read - modify - write mode exit read - modify - write mode. ram column address before entering the mode will be restored. after por, read - modify - write mode is off. 11100011 nop command for no operation 1111 * * * * set test mode reserved for ic testing. do not use. 10101110 10100101 set sleep mode sleep mode will be entered with two commands : command 1: turns off oled panel command 2: set entire display on 13/26 rev. 1.0
bit pattern command description 10101000 **x 5 x 4 x 3 x 2 x 1 x 0 set multiplex ratio to select multiplex ratio n from 2 to the maximum multiplex ratio (por value) (including icon line). max. mux ratio: 65 n= x 5 x 4 x 3 x 2 x 1 x 0 +2, e.g. n=001111b+2=17 10101010 *10x 4 x 3 x 2 x 1 x 0 set frame frequency frame frequency is set by the following formula: x 4 x 3 x 2 x 1 x 0 =00001: frame frequency = 4xn osc f x 4 x 3 x 2 x 1 x 0 =00010: frame frequency = 6xn osc f x 4 x 3 x 2 x 1 x 0 =00011: frame frequency = 8xn osc f where n is mux ratio set by the ?set multiplex ratio? command. por values are 6x65 osc f for n=65, and 8x49 osc f for n= 49 10101011 10x 5 0x 3 00x 0 set bias current mode s et bias current level of segment output cell x 5 =0 and x 3 =1 and x 0 =0: normal (por) x 5 =1 and x 3 =0 and x 0 =1: set low bias current level 1101000x 0 set icon mode x 0 =0: icon mode off (por) x 0 =1: icon mode on 11010011 **x 5 x 4 x 3 x 2 x 1 x 0 set display offset x 5 x 4 x 3 x 2 x 1 x 0 :000000=no scroll by row (por) . . . . . . 111111=scroll by 63 rows 11011000 00000x 2 0x 0 set low power display mode x 2 =0 and x 0 =0: normal (por) x 2 =1 and x 0 =1: set low power consumption 11011001 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 set precharge period x 7 x 6 x 5 x 4 : set precharge period (por=1000) [invalid entry for x 7 x 6 x 5 x 4 =0001 or 0000] x 3 x 2 x 1 x 0 =1000: normal (por) x 3 x 2 x 1 x 0 =0011: for low precharge period usage 11011010 ***1**x 1 0 set current mode x 1 =0: select half range curren t mode (por) x 1 =1: select full range current mode note: remark ?*? stands for ?don?t care? read command table (d/c#=0, r/w#(wr#)=1, e(rd#)=1 for 6800 or e(rd#)=0 for 8080) bit pattern command description d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 status register read d 7 =0: indicates the driver is ready for command. d 7 =1: indicates the driver is busy. d 6 =0: indicates reverse segment mapping with column address d 6 =1: indicates normal segment mapping with column address d 5 =0: indicates the display is on d 5 =1: indicates t he display is off d 4 =0: initialization is not in progress d 4 =1: initialization is in progress after res# or software reset note: patterns other than that given in command table are prohibited to enter to the chip as a command; otherwise, unexpected resul t will occur. 14/26 rev. 1.0
15/26 rev.1.0 6. optical characteristics 6.1 optical characteristics v lcd =16.8v ta=25 ?? item symbol condition min. typ. max. unit main -40--+35 | x | y =0 ?? sub -60--36 main -30--+30 viewing angle | y c r 2 | x =0 ?? sub -42--40 deg contrast ratio c r | x =0 ?? | y =0 ?? 30 50 60 -- turn on t on - - 150 response time turn off t off | x =0 ?? | y =0 ?? - - 100 ms x - 0.43 - - red y | x =0 ?? | y =0 ?? - 0.35 - - x - 0.32 - - green y | x =0 ?? | y =0 ?? - 0.46 - - x - 0.22 - - color of cie coord- inate blue y | x =0 ?? | y =0 ?? - 0.26 - -
16/26 6.2 definition of optical characteristics 6.2.1 definition of viewing angle top top bottom bottom 6.2.2 definition of contrast ratio brightness state selected brightness state unselected = b2/b1 = ratio contrast measuring conditions: 1) ambient temperature: 25 ?? ; 2) frame frequency: 70.0hz 6.2.3 definition of response time turn on time: t on = t d + t r turn off time: t off = t d + t f measuring condition: 1) operating voltage:main-lcd 16.8v sub-lcd 9v 2) frame frequency: 70.0hz
17/26 rev.1.0 6 .3 brightness characteristic item symbol condition min. typ. max. unit brightness bp 100 - - cd/m 2 uniformity ? bp ta=25 ?? 3 ?? 30-80%rh - - 60 % note: 1. the data is measured after leds are turned on for 5 minutes. 2. testing conditions led: v led = 270 v (ac) lcd: all dots are on (white color) 3. brightness in the center of the lcd panel. 4. definition of uniformity ( ? bp) ? bp = bp (min.) / bp (max.) x 100 (%) bp (max.) = maximum brightness in 9 measurement spots bp (min.) = minimum brightness in 9 measurement spots
18/26 rev.1.0 7. reliability 7.1 content of reliability test ta=25 ?? no. test item content of test test condition 1 high temperature storage endurance test applying the high storage temperature for a long time 80 ?? 2 ?? 240h restore 4h at 25 ?? 2 low temperature storage endurance test applying the low storage temperature for a long time -30 ?? 2 ?? 240h restore 4h at 25 ?? 3 high temperature /humidity storage endurance test applying the high temperature and high humidity storage for a long time 70 ?? 2 ?? 90%rh 240h restore 4h at 25 ?? 4 temperature cycle endurance test applying the low and high temperature cycle -30 ????? 25 ????? 80 ????? 25 ?? 30min 5min 30min 5min ??????????????? 1 cycle -30 ?? /80 ?? 10 cycles restore 4h at 25 ?? 5 vibration test (package state) endurance test applying the vibration during transportation 10hz~150hz, 100m/s 2 , 120min 6 shock test (package state) endurance test applying the shock during transportation half- sine wave, 300m/s 2 , 18ms 7 atmospheric pressure test endurance test applying the atmospheric pressure during transportation by air 25kpa 16h restore 2h
19/26 rev.1.0 7.2 failure judgment criterion test item no. criterion item 12 3 4 56789 failure judgement criterion basic specification out of the basic specification electrical specification out of the electrical specification mechanical specification out of the mechanical specification optical characteristic out of the optical specification note for test item refer to 8.1 remark basic specification = optical specification + mechanical specification
20/26 rev.1.0 8. quality level inspection examination or test at t a =25 ?? (unless otherwise stated) min. max. unit il aql external visual inspection under normal illumination and eyesight condition, the distance between eyes and lcd is 25cm. see appendix a ii major 1.0 minor 2.5 display defects under normal illumination and eyesight condition, display on inspection. see appendix b ii major 1.0 minor 2.5 note: major defects: open segment or co mmon, short, serious damages, leakage miner defects: others sampling standard conforms to gb2828
21/26 rev.1.0 9. precautions for use of lcd modules 9.1 handling precautions 10.1.1 the display panel is ma de of glass. do not subject it to a mechanical shock by dropping it from a high place, etc. 9.1.2 if the display panel is dama ged and the liquid crystal substance inside it leaks out, be sure not to get any in your mouth, if the substance comes into contact with your skin or clothes, promptly wash it off using soap and water. 9.1.3 do not apply excessive force to the display surface or the adjoining areas since this may cause the color tone to vary. 9.1.4 the polarizer covering the display surface of the lcd m odule is soft and easily scratched. handle this polarizer carefully. 9.1.5 if the display surface is contaminated, breathe on the surface and gently wipe it with a soft dry cloth. if s till not completely clear, moisten cloth with one of the following solvents: ?a isopropyl alcohol ?a ethyl alcohol solvents other than those men tioned above may damage the polarizer. especially, do not use the following: ?a water ?a ketone ?a aromatic solvents 9.1.6 do not attempt to disassemble the lcd module. 9.1.7 if the logic circuit power is off, do not apply the input signals. 9.1.8 to prevent destruction of the elements by static electricity, be careful to maintain an optimum work environment. a. be sure to ground the body when handling the lcd modules. b. tools required for assembly, su ch as soldering irons, must be properly ground. c. to reduce the amount of sta tic electricity gene rated, do not conduct assembly and other work under dry conditions. d. the lcd module is coated with a film to protect the display surface. be care when peeling off this protectiv e film since static electricity may be generated.
22 /26 rev.1.0 9.2 storage precautions 9.2.1 when storing the lcd modules, avoid exposure to direct sunlight or to the light of fluorescent lamps. 9.2.2 the lcd m odules should be stored under the storage temperature range. if the lcd modules will be stored for a long time, the recommend condition is: temperature : 0 ?? ?? 40 ?? relatively humidity: ? 80% 9.2.3 the lcd modules should be stored in the room without acid, alkali and harmful gas. 9.3 the lcd modules should be no falling and violent shocking during transportation, and also should avoid excessive press, water, damp and sunshine.
23 /26 rev.1.0 appendix a inspection items and criteria for appearance defects items contents criteria leakage not permitted rainbow according to the limit specimen wrong polarizer attachment not permitted not counted max. 3 defects allowed polarizer bubble between polarizer and glass <0.3mm 0.3mm ? ? 0.5mm scratches of polarizer according to the limit specimen not counted max. 3 spots allowed x<0.2mm 0.2mm ? x ? 0.5mm black spot (in viewing area) x=(a+b)/2 not counted max. 3 lines allowed black line (in viewing area) a<0.02mm 0.02mm ? a ? 0.05mm b ? 2.0mm max. 3 spots (lines) allowed progressive cracks not permitted
24 /26 rev.1.0 appendix a inspection item and criteria for appearance defects (continued) items contents criteria a b c ? 3mm ? w/5 ? t / 2 cracks on pads ? 2mm ? w/5 t/2 25/26 rev.1.0 appendix b inspection items and criteria for display defects items contents criteria open segment or open common not permitted short not permitted wrong viewing angle not permitted contrast radio uneven according to the limit specimen crosstalk according to the limit specimen not counted max.3 dots allowed x<0.1mm 0.1mm ? x ? 0.2mm x=(a+b)/2 not counted max.2 dots allowed pin holes and cracks in segment (dot) a<0.1mm 0.1mm ? a ? 0.2mm d<0.25mm max.3 dots allowed not counted max.3 spots allowed x<0.1mm 0.1mm ? x ? 0.2mm black spot (in viewing area) x=(a+b)/2 not counted max.3 lines allowed black line (in viewing area) a<0.02mm 0.02mm ? a ? 0.05mm b ? 0.5mm max.3 spots (lines) allowed
26/26 rev.1.0 appendix b inspection items and criteria fo r display defects (continued) items content criteria not counted max. 2 defects allowed x ? 0.1mm 0.1mm ? x ? 0.2mm x=(a+b)/2 not counted max. 1 defects allowed a ? 0.1mm 0.1mm ? a ? 0.2mm d>0 max.3 defects allowed transfor- mation of segment max.2 defects allowed 0.8w ? a ? 1.2w a=measured value of width w=nominal value of width

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